Various types of three-dimensional (3-D) non-volatile memory devices, and methods for programming such devices, are known in the art. For example, U.S. Patent Application Publication 2012/0069657, whose disclosure is incorporated herein by reference, describes a memory device that includes a memory cell array, in some embodiments a three-dimensional Flash memory, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
U.S. Patent Application Publication 2012/0069664, whose disclosure is incorporated herein by reference, describes a Flash memory system and a word line interleaving method thereof. The Flash memory system includes a memory cell array, such as a three-dimensional array, and word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different word lines and programs data, including the interleaved data, to the memory cell array.
U.S. Patent Application Publication 2013/0028027, whose disclosure is incorporated herein by reference, describes a 3-D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel.
U.S. Pat. No. 8,036,043, whose disclosure is incorporated herein by reference, describes a non-volatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines. Memory cell strings are vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.
U.S. Pat. No. 8,203,882, whose disclosure is incorporated herein by reference, describes a non-volatile semiconductor storage device. When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.
U.S. Pat. No. 8,004,885, whose disclosure is incorporated herein by reference, describes a driving method of a three-dimensional memory device having a plurality of layers. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.